Shreedutt C. Hegde
Hardware and FPGA system design
RESUME
Research
experience​
Summer Intern
The University of Toronto,Canada
Mitacs Globalink Research Internship
​June 2015 - August 2015
-
Fully-funded internship project, at University of Toronto, Canada for 12 weeks,under supervision of Dr. Roman Genov.
-
Set up a wireless link between a PC, and a brain implant PCB designed for epilepsy detection and termination.
-
Involved developing a custom firmware, in C language, for the USB dongle plugged to a PC, writing Verilog code for the FPGA that controlled the RFIC on brain implant PCB, and MATLAB scripting for real-time plot of recorded brain signals.
Undergraduate Researcher
VIT University, Vellore, India
​January 2016 - May 2016
-
​Final Year project work, under the supervision of Prof. Boopalan G., in the Communications Lab, VIT University.
-
Involved System level designing and implementation of Software Defined Radio, with a full user-configurable baseband stage.
-
Developed a baseband signal generator for MAX2830 RF front end chipset,using an Altera Cyclone-4 FPGA, which received digital baseband signals from MATLAB, and designed a digital to analog interface board to feed signals to the RF chipset.
Education
Carnegie Mellon University,Pittsburgh,USA
Master of Science in Electrical and Computer Engineering
Sept 2016-Dec 2017
CGPA: 3.56 (on 4-point scale) .
Focused on hardware software co-design, with courses in Reconfigurable Logic, Parallel Computer architecture, system software, and Computer vision.
​
VIT University,Vellore,India.
​B.Tech. in Electronics and Communication Engineering
2012 - 2016
CGPA: 9.01(on 10-point scale) .
Coming here proved to be life changing experience, transforming myself from a not-so-expressive person, to a confident and focussed individual. Developed a solid interest for electronic and computer systems that motivated me to aspire for a career in hardware systems design.
​
DAV Public School Aundh,Pune,India.
Class 12th CBSE Board Examination.
2010-2012
Percentage: 94.8%
City International School Aundh,Pune,India.
Class 10th CBSE Board Examination
2005-2010
Percentage: 96.8%
Industry
experience​
Summer Intern
The University of Toronto,Canada
Mitacs Globalink Research Internship
​June 2015 - August 2015
-
Fully-funded internship project, at University of Toronto, Canada for 12 weeks,under supervision of Dr. Roman Genov.
-
Set up a wireless link between a PC, and a brain implant PCB designed for epilepsy detection and termination.
-
Involved developing a custom firmware, in C language, for the USB dongle plugged to a PC, writing Verilog code for the FPGA that controlled the RFIC on brain implant PCB, and MATLAB scripting for real-time plot of recorded brain signals.
Undergraduate Researcher
VIT University, Vellore, India
​January 2016 - May 2016
-
​Final Year project work, under the supervision of Prof. Boopalan G., in the Communications Lab, VIT University.
-
Involved System level designing and implementation of Software Defined Radio, with a full user-configurable baseband stage.
-
Developed a baseband signal generator for MAX2830 RF front end chipset,using an Altera Cyclone-4 FPGA, which received digital baseband signals from MATLAB, and designed a digital to analog interface board to feed signals to the RF chipset.
Technical Skills(HW)
-
FPGA: Altera Cyclone | Actel Igloo | Xilinx 7 series
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PSoC: Xilinx Zedboard , PYNQ Z1
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Arduino UNO.
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AVR ATMega Series microcontroller.
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Intel 8051 based SoC controllers.
Technical Skills(SW)
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Linux and open source tools.
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Data analytics - Pandas
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ModelSIM/QuestaSim
Programming Languages
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(System) Verilog HDL.
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C.
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Python.